The device has 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes). Data in the page mode can be read out at 25ns cycle .
• Flexible & Efficient Memory Architecture
- Memory Cell: 1bit/Memory Cell - Organization: 512Mb x8, 256Mb x16 - Page Size for x8: (4K + 256) Bytes - Page Size for x16: (2K + 128) words - Block Size for x8: 64x (4K + 256) Bytes - Block Size for x16: 64x (2K + 128) words - Number of Plane = 1 - Number of Block per Die (LUN) = 2048
• Highest performance - Read Performance:
- Random Read: 25us (Max.) - Serial Access: 25ns (Max.)
- Write Performance:
- Program time: 300us (typ.), 700us (max.) - Block Erase time: 3.5ms (typ.), 10ms (max.)
• Voltage and Temp. Ranges - Single 3.3V (2.7V to 3.6V) Volt.
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