HY5DU56422AT Datasheet

HY5DU56422AT (HY5DU56xx22A(L)T) 256M-S DDR SDRAM

and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (.

Features

•
•
•
•
•
•
• VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
•
•
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 1.5, 2, 2.5 and 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode et4U.com
• Internal four bank operations with single pulsed /RAS x16 device has two byt.