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The SY10/100H607 are 6-bit, registered, dual supply PECL-to-TTL translators. The devices feature differential PECL inputs for both data and clock. The TTL outputs feature 48mA sink, 15mA source drive capability for driving high fanout loads. The asynchronous master reset control is a PECL level inpu.
s Differential PECL data and clock inputs s 48mA sink, 15mA source TTL outputs s Single +5V power supply s Multiple power and ground pins to minimize noise s Specified within-device skew s VBB output for single-ended use s Fully compatible with MC10H/100H607 s Available in 28-pin PLCC package DESCRIPTION The SY10/100H607 are 6-bit, registered, dual supply PECL-to-TTL translators. The devices feature differential PECL inputs for both data and clock. The TTL outputs feature 48mA sink, 15mA source drive capability for driving high fanout loads. The asynchronous master reset control is a PECL lev.
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