| Part Number | HYB39S128400FE |
| Manufacturer | Qimonda |
| Title | 128-MBit Synchronous DRAM |
| Description | The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These... |
| Features |
• • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plas... |
| Datasheet | HYB39S128400FE pdf datasheet |
| Part Number | HYB39S128400FTL |
| Manufacturer | Qimonda |
| Title | 128-MBit Synchronous DRAM |
| Description | The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These. |
| Features |
• • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plas. |
| Datasheet | HYB39S128400FTL pdf datasheet |
| Part Number | HYB39S128400FT |
| Manufacturer | Qimonda |
| Title | 128-MBit Synchronous DRAM |
| Description | The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These. |
| Features |
• • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plas. |
| Datasheet | HYB39S128400FT pdf datasheet |
| Part Number | HYB39S128400FEL |
| Manufacturer | Qimonda |
| Title | 128-MBit Synchronous DRAM |
| Description | The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These. |
| Features |
• • • • • • • • • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plas. |
| Datasheet | HYB39S128400FEL pdf datasheet |
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