The H5TQ4G83CFR-xxC,H5TQ4G63CFR-xxC, H5TQ4G83CFR-xxI, H5TQ4G63CFR-xxI, H5TQ4G83CFR-xxL, H5TQ4G63CFR-xxL,H5TQ4G83CFR-xxJ and H5TQ4G63CFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density a.
and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8 .
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No. | Part # | Manufacture | Description | Datasheet |
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1 | H5TQ4G63CFR-xxC |
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2 | H5TQ4G63CFR-xxI |
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3 | H5TQ4G63CFR-xxL |
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4 | H5TQ4G63AFR-xxC |
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5 | H5TQ4G63AFR-xxI |
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