NPIC6C595-Q100 Datasheet

NPIC6C595-Q100 Power logic 8-bit shift register

The NPIC6C595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset inp.

Features

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +125 C
 Low RDSon
 Eight Power EDNMOS transistor outputs of 100 mA continuous current
 250 mA current limit capability
 Output clamping voltage 33 V
 30 mJ avalanche energy capability
 All registers cleared with single input
 Low power consumption
 ESD protection:
 HBM AEC-Q100-002 revision D exceeds 2500 V
 CDM AEC-Q100-011 revision B exceeds 1000 V 3. Applications
 LED sign
 Graphic status panel Nexperia NPIC6C595-Q100 Power logic 8-bit shift register; open-drain outputs
 Faul.