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XC2C128 Datasheet

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XC2C128 CoolRunner-II CPLD

Product Specification Description The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, o.

Features


• Optimized for 1.8V systems - As fast as 5.7 ns pin-to-pin delays - As low as 13 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options - 100-pin VQFP with 80 user I/O - 144-pin TQFP with 100 user I/O - 132-ball CP (0.5mm) BGA with 100 user I/O - Pb-free available for all packages
• Advanced system features - Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger inpu.

XC2C128 XC2C128 XC2C128

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