Differential LVPECL Crystal Clock Oscillators HPK5361 Series 200 fsec Jitter +2.5V +3.3V “K” Family Femto second integrated phase jitter (200 fs typical, 12 KHz to 20 MHz) Superior phase noise (-138 dBc/Hz at 10 KHz and -144 dBc/Hz at 100 KHz offset). High performance with surprisingly low pri.
tom, use “temperature range code + desired stability in ppm” for the stability code. Example: “C20” (±20 ppm over -10 to +70°C). +2.5 V ± 5 % (Voltage code is “25”); or +3.3 V ± 5 % (Voltage code is “3”) VDD-1.025 V min.; VDD-0.95 V typical; VDD-0.88 V max. Condition: 50 ohms to VDD-2V VDD-1.810 V min.; VDD-1.70 V typical; VDD-1.62 V max. Condition: 50 ohms to VDD-2V 595 mV min; 750 mV typical; 930 mV max. 35 mA typical; 50 mA max. 50 ohms into VCC-2V or Thevenin equivalent (terminating resistors required on all outputs). 0.3 n sec. typ; 0.5 n sec. max. 20%Æ80% of waveform 0.3 n sec. typ; 0.5 .
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