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MC10EL01 Datasheet PDF

Motorola
Part Number MC10EL01
Manufacturer Motorola
Title 4-input OR/NOR
Description PIN D0–D3 Q FUNCTION Data Inputs Data Outputs DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) –40°C 0°C 25°C 85°C Symbol Chara...
Features ...

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Datasheet PDF File MC10EL01 PDF File


MC10EL01 MC10EL01 MC10EL01




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MC10E016 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8ĆBit Synchronous Binary Up Counter MC10E016 MC100E016 The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC.

MC10E016 : The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H™ family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated.

MC10E101 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. • 500ps Max. Propagation Delay • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D3a D3b D3c D3d VCCO Q3 Q3 25 24 23 22 21 20 19 D2d 26 18 Q2 D2c 27 17 Q2 D2b 28 16 VCC VEE 1 15 Q1 D2a 2 14 Q1 D1d 3 13 Q0 D1c 4 12 Q0 5 6 7 8 9 10 11 D1b D1a D0d D0c D0b D0a VCCO * All VCC and VCCO pins are tied together on the die. MC10E101 MC100E101 QUAD 4-INPUT OR/NOR GATE FN SUFFIX PLASTIC PACKAGE CASE 776-02 12/93 © Motorola, Inc. 1996 LOGIC DIAGRAM D0a D0b Q0 D0c Q0 D0d D1a D1b Q1 D1c Q1 D1d D2a D2b Q2 D2c Q2 D2d.

MC10E101 : The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: ♦ Human Body Model; 2 kV ♦ Machine Model; 200 V • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb-Free) • Flammability Rating: ♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 115 devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com PLCC−28 FN SUFFIX CASE 776−02.

MC10E104 : The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features • 600 ps Max. Propagation Delay • OR/NOR Function Outputs • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: ♦ 2 kV Human Body Model ♦ 200 V Machine Model • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see .

MC10E104 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. • 600ps Max. Propagation Delay • OR/NOR Function Outputs • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D3a D4b D4a NC VCCO F F 25 24 23 22 21 20 19 D3b 26 18 Q4 D2a 27 17 Q4 D2b 28 16 VCC VEE 1 15 Q3 D1a 2 14 Q3 D1b 3 13 Q2 D0a 4 12 Q2 5 6 7 8 9 10 11 D0b VCCO Q0 Q0 Q1 Q1 VCCO * All VCC and VCCO pins are tied together on the die. PIN NAM.

MC10E107 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2ĆInput XOR/XNOR Gate The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. • 600ps Max. Propagation Delay • OR/NOR Function Outputs • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D3a D4b D4a 25 24 23 D3b 26 NC VCCO F 22 21 20 F 19 18 Q4 D2a 27 17 Q4 D2b 28 16 VCC VEE 1 15 Q3 D1a 2 14 Q3 D1b 3 13 Q2 D0a 4 12 Q2 5 6 7 8 9 10 11 D0b VCCO Q0 Q0 Q1 Q1 VCCO * All VCC and VCCO pins are tied together on the die. PIN NAMES Pi.

MC10E107 : The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features http://onsemi.com • 600 ps Maximum Propagation Delay • OR/NOR Function Outputs • PECL Mode Operating Range: • NECL Mode Operating Range: • • • • VCC = 4.2 V to 5.7 V with VEE = 0 V PLCC−28 FN SUFFIX CASE 776 • • • VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; 2 kV, Machine Model; 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensi.

MC10E111 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1:9 Differential Clock Driver The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. • Low Skew • Guarateed Skew Spec • Differential Design • VBB Output • Enable • Extended 100E VEE Range of –4.2 to –5.46V • 75kΩ Input Pulldown Resistors The device is specifically designed, modeled and produced with low skew as the key goal..

MC10E111 : The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a d.

MC10E112 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock driver, although the MC10E/100E111 is designed specifically for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the E212 device. • 600ps Max. Propagation Delay • Common Enable Input • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors MC10E112 MC100E112 QUAD DRIVE.

MC10E112 : The MC10E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock driver, although the MC10E/100E111 is designed specifically for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the E212 device. The 100 Series contains temperature compensation. Features • 600 ps Max. Propagation Delay • Common Enable Input • PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = .

MC10E116 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint Differential Line Receiver MC10E116 MC100E116 The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. An internally generated reference supply (VBB) is available for single-ended reception. • 500ps Max. Propagation Delay • VBB Supply Output • Dedicated VCCO Pin for Each Receiver • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors QUINT DIFFERENTIAL LINE RECEIVER Active current sources plus a deep collector feature of the MOSAIC III process provide the receivers with excellent common-mode noise rejection. Each receiver has a dedicated VCCO supply lead, providing optimum symmetry and sta.

MC10E116 : The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest. Active current sources plus a deep collector feature of the MOSAIC III process provide the receivers with excellent common-mode noise rejection. Each receiver has a dedicated VCCO supply lead, providing optimum symmetry and stability. If both inverting and non-inverting inputs are at an equal potential of −2.5 V, the receiver does not go to a defined state, but rather current-shares in normal differential amplifier fashion, producing output voltage levels midway between HIGH and LOW, or the device.

MC10E122 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9ĆBit Buffer The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. • 500ps Max. Propagation Delay • Extended 100E VEE Range of – 4.2V to – 5.46 V • 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D8 NC NC VCCO NC Q8 VCCO 25 24 23 22 21 20 19 D7 26 18 Q7 D6 27 17 Q6 D5 28 16 VCC VEE 1 15 Q5 D4 2 D3 3 D2 4 14 Q4 13 VCCO 12 Q3 5 6 7 8 9 10 11 D1 D0 VCCO Q0 Q1 VCCO Q2 * All VCC and VCCO pins are tied together on the die. PIN NAMES Pin D0 – D8 Q0 – Q8 Data Inputs Data Outputs Function MC10E122 MC100E122 9-BIT BUFFER FN SUFFIX PLASTIC PACKAGE CASE 776-02 LOGIC DIAGRAM D0 Q0 D1 Q1 D2 Q2 D3 Q3 D.

MC10E122 : The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. Features http://onsemi.com • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • • • • • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 KW Pulldown Resistors ESD Protection: Human Body Model; 2 kV, Machine Model; 200 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count =.

MC10E131 : The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE are LOW, and transfers to the slave when either CC or CE (or both) go HIGH. .




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