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OR22


Part Number OR22
Manufacturer AMI
Title CMOS Gate Array
Description OR2x is a family of 2-input gates which perform the logical OR function. Logic Symbol Truth Table OR2x A Q B A Q B A BQ LLL LHH HLH HHH HDL S...
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Datasheet OR22 PDF File








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OR2 : www.DataSheet4U.com R Austria Mikro Systeme International OR2 CUB 0.6 µm CMOS OR2 is a 2-input OR gate with 1x drive strength. Truth Table A L L H H B L H L H Q L H H H Capacitance Ci (pF) A OR2 Q A B 0.037 0.036 B Area 0.54 mils2 Power 2.09 µW / MHz Delay [ns] = tpd.. = f(SL, L) Output Slope [ns] = op_sl.. = f(L) AC Characteristics : Tj = 25°C with SL = Input Slope [ns] ; L = Output Load [pF] with L = Output Load [pF] Typical Process VDD = 3.3V AC Characteristics Characteristics Symbol tpdar tpdaf tpdbr tpdbf op_slar op_slaf op_slbr op_slbf SL = 0.1 L = 0.1 L = 0.7 L = 1.0 L = 0.1 SL = 2.0 L = 0.7 L = 1.0 Delay A to Q Delay B to Q Output Slope A to Q Output Slope B to Q 0.

OR21 : OR2x is a family of 2-input gates which perform the logical OR function. Logic Symbol Truth Table OR2x A Q B A Q B A BQ LLL LHH HLH HHH HDL Syntax Verilog .. OR2x inst_name (Q, A, B); VHDL.... inst_name: OR2x port map (Q, A, B); Pin Loading Pin Name A B OR21 1.0 1.0 Equivalent Loads OR22 OR24 1.0 2.1 1.0 2.1 OR26 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) OR21 OR22 2.0 2.0 TBD TBD 2.6 3.6 OR24 OR26 4.0 5.0 TBD TBD 7.3 10.7 a. See page 2-15 for power equation. 3-211 25[ $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ.

OR22 : R Austria Mikro Systeme International OR22 CUB 0.6 µm CMOS OR22 is a 2-input OR gate with 2x drive strength. Truth Table A L L H H B L H L H Q L H H H Capacitance Ci (pF) A OR22 Q A B 0.038 0.036 B Area 0.54 mils2 Power 3.68 µW / MHz Delay [ns] = tpd.. = f(SL, L) Output Slope [ns] = op_sl.. = f(L) AC Characteristics : Tj = 25°C with SL = Input Slope [ns] ; L = Output Load [pF] with L = Output Load [pF] Typical Process VDD = 3.3V AC Characteristics Characteristics Symbol tpdar tpdaf tpdbr tpdbf op_slar op_slaf op_slbr op_slbf SL = 0.1 L = 0.2 L = 1.4 L = 2.0 L = 0.2 SL = 2.0 L = 1.4 L = 2.0 Delay A to Q Delay B to Q Output Slope A to Q Output Slope B to Q 0.51 0.51 0.53 0.54.

OR22 : R Austria Mikro Systeme International OR22 CUB 0.6 µm CMOS OR22 is a 2-input OR gate with 2x drive strength. Truth Table A L L H H B L H L H Q L H H H Capacitance Ci (pF) A OR22 Q A B 0.038 0.036 B Area 0.54 mils2 Power 3.68 µW / MHz Delay [ns] = tpd.. = f(SL, L) Output Slope [ns] = op_sl.. = f(L) AC Characteristics : Tj = 25°C with SL = Input Slope [ns] ; L = Output Load [pF] with L = Output Load [pF] Typical Process VDD = 3.3V AC Characteristics Characteristics Symbol tpdar tpdaf tpdbr tpdbf op_slar op_slaf op_slbr op_slbf SL = 0.1 L = 0.2 L = 1.4 L = 2.0 L = 0.2 SL = 2.0 L = 1.4 L = 2.0 Delay A to Q Delay B to Q Output Slope A to Q Output Slope B to Q 0.51 0.51 0.53 0.54.

OR24 : OR2x is a family of 2-input gates which perform the logical OR function. Logic Symbol Truth Table OR2x A Q B A Q B A BQ LLL LHH HLH HHH HDL Syntax Verilog .. OR2x inst_name (Q, A, B); VHDL.... inst_name: OR2x port map (Q, A, B); Pin Loading Pin Name A B OR21 1.0 1.0 Equivalent Loads OR22 OR24 1.0 2.1 1.0 2.1 OR26 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) OR21 OR22 2.0 2.0 TBD TBD 2.6 3.6 OR24 OR26 4.0 5.0 TBD TBD 7.3 10.7 a. See page 2-15 for power equation. 3-211 25[ $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ.

OR26 : OR2x is a family of 2-input gates which perform the logical OR function. Logic Symbol Truth Table OR2x A Q B A Q B A BQ LLL LHH HLH HHH HDL Syntax Verilog .. OR2x inst_name (Q, A, B); VHDL.... inst_name: OR2x port map (Q, A, B); Pin Loading Pin Name A B OR21 1.0 1.0 Equivalent Loads OR22 OR24 1.0 2.1 1.0 2.1 OR26 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) OR21 OR22 2.0 2.0 TBD TBD 2.6 3.6 OR24 OR26 4.0 5.0 TBD TBD 7.3 10.7 a. See page 2-15 for power equation. 3-211 25[ $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ.

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