S7I161884M Datasheet

S7I161884M 512Kx36 & 1Mx18 DDRII CIO BL4 SRAM

The S7I163684M and S7I161884M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7I163684M and 1,048,576 words by 18 bits for S7I161884M. Address, data inputs, and all control signals are synchronized to the input clock (K or K). .

Features

•1.8V+0.1V/-0.1V Power Supply.
•DLL circuitry for wide output data valid window and future fre- quency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O
•Pipelined, double-data rate operation.
• Common data input/output bus.
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR (Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
•Tw.