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CD54HCT14


Part Number CD54HCT14
Manufacturer Texas Instruments
Title Hex Inverting Schmitt Trigger
Description • Unlimited Input Rise and Fall Times • Exceptionally High Noise Immunity • Fanout (Over Temperature Range) - Standard Outputs ...
Features Description
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
• Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads
• Wide Operating Temperature Range -55oC to 12...

File Size 1.66MB
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CD54HCT11 : • Buffered Inputs • Typical Propagation Delay: CL = 15pF, TA = 25oC 8ns at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC11 and ’HCT11 .

CD54HCT112 : • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Set and Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Lo.

CD54HCT123 : The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B..

CD54HCT125 : • Three-State Outputs • Separate Output Enable Inputs • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC125 and ’HCT125 contain 4 independent three-state buffers, .

CD54HCT126 : • Three-State Outputs • Separate Output Enable Inputs • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC126 and ’HCT126 contain four independent threestate buffers.

CD54HCT132 : This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT132M SOIC (14) 8.65 mm × 3.90 mm CD74HCT132E PDIP (14) 19.30 mm × 6.40 mm CD54HCT132J CDIP (14) 19.94 mm × 7.62 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y Device functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyD-corcitui.

CD54HCT132J : This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT132M SOIC (14) 8.65 mm × 3.90 mm CD74HCT132E PDIP (14) 19.30 mm × 6.40 mm CD54HCT132J CDIP (14) 19.94 mm × 7.62 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y Device functional pinout CopyrighAtn©I2M0P21OTReTxaAsNInTsNtruOmTeInCtsEInactotrhpeoreatnedd of this data sheet addresses availability, warranty, changes, use iSnusbamfeittyD-corcitui.

CD54HCT138 : The CDx4HC(T)138 and '238 are three to eight decoders with one standard output strobe (G2) and two active low output strobes (G 1 and G 0). When the outputs are gated by any of the strobe inputs, they are all forced into the high state. When the outputs are not disabled by the strobe inputs, only the selected output is low while all others are high. The CDx4HC(T)238 is a three to eight decoder with one standard output strobe (G2) and two active low output strobes (G 1 and G 0). When the outputs are gated by any of the strobe inputs, they are all forced into the low state. When the outputs are not disabled by the strobe inputs, only the selected output is high while all others are low. PAR.

CD54HCT138F : The CDx4HC(T)138 and '238 are three to eight decoders with one standard output strobe (G2) and two active low output strobes (G 1 and G 0). When the outputs are gated by any of the strobe inputs, they are all forced into the high state. When the outputs are not disabled by the strobe inputs, only the selected output is low while all others are high. The CDx4HC(T)238 is a three to eight decoder with one standard output strobe (G2) and two active low output strobes (G 1 and G 0). When the outputs are gated by any of the strobe inputs, they are all forced into the low state. When the outputs are not disabled by the strobe inputs, only the selected output is high while all others are low. PAR.

CD54HCT139 : The ’HC139 and ’HCT139 devices contain two independent binary to one of four decoders each with a single active low enable input (1E or 2E). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally high outputs to go low. If the enable input is high all four outputs remain high. For demultiplexer operation the enable input is the data input. The enable input also functions as a chip select when these devices are cascaded. This device is functionally the same as the CD4556B and is pin compatible with it. The outputs of these devices can drive 10 low power Schottky TTL equivalent loads. The HCT logic family is functionally as well as pin equivalent to the LS logic .

CD54HCT151 : • Complementary Data Outputs • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • Alternate Source is Philips/Signetics • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC151 and ’HCT151.

CD54HCT153 : • Common Select Inputs • Separate Enable Inputs • Buffered inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs . 15 LSTTL Loads • Wide Operating Temperature Range -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC153 and ’HCT153 are dual 4- to 1-lin.

CD54HCT154 : A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low. Ordering Information PART NUMBER CD54HC154F3A CD54HCT154F3A CD74HC154E CD74HC154EN CD74HC154M CD74HC154M96 CD74HCT154E CD74HCT154EN CD74HCT154M CD74HCT154M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 24 Ld CERDIP 24 Ld CERDIP 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC The ’HC154 and ’HCT154 .




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