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CD74HC173


Part Number CD74HC173
Manufacturer Texas Instruments
Title Quad D-Type Flip-Flop
Description The CDx4HC173 and CDx4HCT173 contains four independent D-type flip-flops with shared clock (CP), reset (MR), and data enable (E1, E2) pins. PART...
Features
• Three-state buffered outputs
• Gated input and output enables
• Fanout (over temperature range)
  – Standard outputs : 10 LSTTL loads
  – Bus driver outputs : 15 LSTTL loads
• Wide Operating Temperature Range : -55°C to 125°C
• Balanced propagation delay and transition times
• Significant power and re...

File Size 1.11MB
Datasheet CD74HC173 PDF File








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CD74HC173E : The CDx4HC173 and CDx4HCT173 contains four independent D-type flip-flops with shared clock (CP), reset (MR), and data enable (E1, E2) pins. PART NUMBER Device Information PACKAGE(1) BODY SIZE (NOM) CD54HC173F CDIP (16) 21.34 mm × 6.92 mm CD54HCT173F3A CDIP (16) 21.34 mm × 6.92 mm CD74HC173E PDIP (16) 19.31mm × 6.35 mm CD74HCT173E PDIP (16) 19.31mm × 6.35 mm CD74HC173M SOIC (16) 9.90 mm × 3.90 mm CD74HCT173M SOIC (16) 9.90 mm × 3.90 mm CD74HC173PW TSSOP (16) 5.00 mm × 4.40 mm (1) For all packages see the orderable addendum at the end of the data sheet.. Shared Control Logic One of Four D-Type Flip-Flops DQ Qx Dx R Functional Block Diagram An IMPORTANT NOTICE at the .

CD74HC173M : The CDx4HC173 and CDx4HCT173 contains four independent D-type flip-flops with shared clock (CP), reset (MR), and data enable (E1, E2) pins. PART NUMBER Device Information PACKAGE(1) BODY SIZE (NOM) CD54HC173F CDIP (16) 21.34 mm × 6.92 mm CD54HCT173F3A CDIP (16) 21.34 mm × 6.92 mm CD74HC173E PDIP (16) 19.31mm × 6.35 mm CD74HCT173E PDIP (16) 19.31mm × 6.35 mm CD74HC173M SOIC (16) 9.90 mm × 3.90 mm CD74HCT173M SOIC (16) 9.90 mm × 3.90 mm CD74HC173PW TSSOP (16) 5.00 mm × 4.40 mm (1) For all packages see the orderable addendum at the end of the data sheet.. Shared Control Logic One of Four D-Type Flip-Flops DQ Qx Dx R Functional Block Diagram An IMPORTANT NOTICE at the .

CD74HC174 : The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flipflops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six masterslave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC174F3A.

CD74HC175 : advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1. Ordering Information PART NUMBER CD54HC175F3A CD54HCT175F3A CD74HC175E CD74HC175M CD74HC175MT CD74HC175M96 CD74HCT175E CD74HCT175M CD74HCT175MT CD74HCT175M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -5.




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