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SNJ54HC10W


Part Number SNJ54HC10W
Manufacturer Texas Instruments
Title TRIPLE 3-INPUT POSITIVE-NAND GATES
Description ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean functi...
Features SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC1...

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SNJ54HC109FK : ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops.

SNJ54HC109J : ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops.

SNJ54HC109W : ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops.

SNJ54HC10FK : ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC10N SN74HC10N Tube of 50 SN74HC10D SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC10J −55°C to 125°C CFP − W Tube of 150 SNJ54HC10W SNJ54.

SNJ54HC10J : ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC10N SN74HC10N Tube of 50 SN74HC10D SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC10J −55°C to 125°C CFP − W Tube of 150 SNJ54HC10W SNJ54.




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