DatasheetsPDF.com

SN74AC241DW Datasheet PDF


Part Number SN74AC241DW
Manufacturer Texas Instruments
Title OCTAL BUFFERS/DRIVERS
Description ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory addre...
Features 995 − REVISED OCTOBER 2003 SN54AC241 J OR W PACKAGE SN54AC241 DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1 1A1 2 2Y4 3 1A2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 GND 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 SN54AC241 FK PACKAGE (TOP VIEW) 2Y4 1A1 1OE V...

File Size 1.34MB
Datasheet SN74AC241DW PDF File








Similar Ai Datasheet

SN74AC240 : These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Package Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) SN54AC240 J (CDIP, 20) W (CFP, 20) 24.2mm x 7.62mm 13.09mm x 8.13mm 24.2mm × 6.92mm 13.09mm × 6.92mm N (PDIP, 20) 24.33mm × 9.4mm 24.33 mm × 6.35 mm DW (SOIC, 20) 12.8mm × 10.3mm 12.8mm × 7.5mm SN74AC240 NS (SOP, 20) 12.6mm × 7.8mm 12.6mm × 5.3mm DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm × 4.4mm (1) For more information, see Section 11. (2) The package size (length × widt.

SN74AC240-Q1 : ordering information This octal buffer and line driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AC240 device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. DW OR PW PACKAGE (TOP VIEW) 1OE 1 1A1 2 2Y4 3 1A2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 GND 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 To ensure the high-impedance state during power up or power down, OE shou.

SN74AC241 : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC241 devices are organized as two 4-bit buffers/drivers with separate complementary output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; t.

SN74AC241N : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC241 devices are organized as two 4-bit buffers/drivers with separate complementary output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; t.

SN74AC241PW : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC241 devices are organized as two 4-bit buffers/drivers with separate complementary output-enable (1OE and 2OE) inputs. When 1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; t.

SN74AC244 : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC244 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN54AC244, SN7.

SN74AC244-EP : This octal buffer and line driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AC244-EP device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA –55°C to 1.

SN74AC244DW : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC244 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN54AC244, SN7.

SN74AC244N : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC244 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN54AC244, SN7.

SN74AC244PW : ordering information These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AC244 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN54AC244, SN7.

SN74AC245 : The 'AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. PART NUMBER SNx4AC245 Device Information PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3mm DW (SOIC, 20) 12.8mm × 10.3mm 12.8mm × 7.5mm N (PDIP, 20) 24.33mm × 9.

SN74AC245-EP : ordering information The SN74AC245 octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. When the output-enable (OE) is low, the device passes noninverted data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction control (DIR) input. A high on OE disables the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDER.

SN74AC245DW : The 'AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. PART NUMBER SNx4AC245 Device Information PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3mm DW (SOIC, 20) 12.8mm × 10.3mm 12.8mm × 7.5mm N (PDIP, 20) 24.33mm × 9.

SN74AC245N : The 'AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. PART NUMBER SNx4AC245 Device Information PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3mm DW (SOIC, 20) 12.8mm × 10.3mm 12.8mm × 7.5mm N (PDIP, 20) 24.33mm × 9.

SN74AC245PW : The 'AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. PART NUMBER SNx4AC245 Device Information PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3mm DW (SOIC, 20) 12.8mm × 10.3mm 12.8mm × 7.5mm N (PDIP, 20) 24.33mm × 9.




Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)