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IDT7028 Datasheet PDF


Part Number IDT7028
Manufacturer Renesas
Title HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM
Description The IDT7028 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT7028 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a com...
Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access
  – Commercial: 15ns (max.)
  – Industrial: 20ns (max.) ◆ Low-power operation
  – IDT7028L Active: 1W (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external log...

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Datasheet IDT7028 PDF File








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IDT7024L : HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM IDT7024S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ Low-power operation – IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ Interrupt Flag ◆ O.

IDT7024S : HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM IDT7024S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ Low-power operation – IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ Interrupt Flag ◆ O.

IDT7025L : HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM IDT7025S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ Low-power operation – IDT7025S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7025L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7025 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ Interrupt Flag ◆ O.

IDT7025S : HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM IDT7025S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ Low-power operation – IDT7025S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7025L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7025 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ Interrupt Flag ◆ O.

IDT70261L : HIGH-SPEED IDT70261S/L 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial 20/25ns (max.) ◆ Low-power operation – IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-c.

IDT70261S : HIGH-SPEED IDT70261S/L 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial 20/25ns (max.) ◆ Low-power operation – IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-c.

IDT7026L : HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM IDT7026S/L LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) – Military: 20/25/35/55ns (max.) ◆ Low-power operation – IDT7026S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7026L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H f.

IDT7026S : HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM IDT7026S/L LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) – Military: 20/25/35/55ns (max.) ◆ Low-power operation – IDT7026S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7026L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H f.

IDT7027L : HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM IDT7027S/L Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns (max.) ◆ Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for bus matching capability. ◆ Dual chip enables allow for depth expansion without external logic Functional Block Diagram R/WL UBL CE0L CE1L OEL LBL ◆ IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH.

IDT7027S : HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM IDT7027S/L Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns (max.) ◆ Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ Separate upper-byte and lower-byte control for bus matching capability. ◆ Dual chip enables allow for depth expansion without external logic Functional Block Diagram R/WL UBL CE0L CE1L OEL LBL ◆ IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH.

IDT7028L : The IDT7028 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT7028 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-ormore word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port .




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