SPC58EN84E7 Datasheet

SPC58EN84E7 32-bit Power Architecture microcontroller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Features

• AEC-Q100 qualified
• 32-bit Power Architecture VLE compliant CPU cores:
  – Five enhanced main e200z4256n3 cores, dual issue, two paired in lockstep
  – Floating Point, End-to-End Error Correction
• 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory:
  – supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
  – Supports read while read between the two code Flash partitions.
• 128 KB on-chip general-purpose SRAM (in addition to 384 KB included in the CPUs)
• 96-channel direct memory access controller (eDMA)
• Comprehensive new generation A.