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IS42S32200N Datasheet PDF


Part Number IS42S32200N
Manufacturer ISSI
Title 64-MBIT SYNCHRONOUS DYNAMIC RAM
Description The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internall...
Features
• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length: (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/I...

File Size 1.04MB
Datasheet IS42S32200N PDF File








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IS42S32200 : A0-A10 Address Input BA0, BA1 Bank Select Address I/O0 to I/O31 Data I/O CLK System Clock Input CKE CS Clock Enable Chip Select RAS Row Address Strobe Command CAS WE Column A.

IS42S32200E : The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capab.

IS42S32200L : The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capabilit.




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