DatasheetsPDF.com

ICS97ULP845A

Part Number ICS97ULP845A
Manufacturer Renesas
Title 1.8V Low-Power Wide-Range Frequency Clock Driver
Description Features: • Low skew, low jitter PLL clock driver • 1 to 5 differential clock distribution (SSTL_18) • Feedback pins for input to output synchroni...
Features
• Low skew, low jitter PLL clock driver
• 1 to 5 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state Switching Characteristics:
• Period jitter: 40ps
• Half-period jit...

File Size 400.86KB
Datasheet ICS97ULP845A PDF File







Similar Datasheet

ICS97ULP845A : Features: • Low skew, low jitter PLL clock driver • 1 to 5 differential clock distribution (SSTL_18) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Auto PD when input signal is at a certain logic state Switching Characteristics: • Period jitter: 40ps • Half-period jitter: 60ps • CYCLE - CYCLE jitter 40ps • OUTPUT - OUTPUT skew: 40ps Pin Configuration 12 3 4 5 A B C D E F 28-Ball BGA Top View Block Diagram OE OS AVDD Powerdown Control and Test Logic LD* or OE LD* PLL bypass CLK_INT CLK_INC 10K-100k GND PLL FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. 1109D—06/19/07 CL.




Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)