ADSP-21564 SHARC+ Single Core High Performance DSP

ADSP-21564 SHARC+ Single Core High Performance DSP

................................................. 3 SHARC Processor ................................................. 4 SHARC+ Core Architecture .................................... 6 System Infrastructure ............................................. 8 System Memory Map .............................

Features

Enhanced SHARC+ high performance floating-point core Up to 933 MHz 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS compliant 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant Low system power across automotive temperature range 3.3 V I/O with no power sequencing requirement ADSP-21560/21561/21564/21568 MEMORY Large o.