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74LVT16652A

NXP

3.3V LVT 16-bit bus transceiver/ register

INTEGRATED CIRCUITS 74LVT16652A 3.3V LVT 16-bit bus transceiver/ register (3-State) Product specification Supersedes da...


74LVT16652A

NXP


Octopart Stock #: O-43151

Findchips Stock #: 43151-F

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Description
INTEGRATED CIRCUITS 74LVT16652A 3.3V LVT 16-bit bus transceiver/ register (3-State) Product specification Supersedes data of 1994 IC23 Data Handbook 1998 Feb 19 Philips Semiconductors Philips Semiconductors Product specification 3.3V 16-bit bus transceiver/register (3-State) 74LVT16652A FEATURES • 16-bit bus interface • 3-State buffers • Ou
More View tput capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model resistors to hold unused inputs DESCRIPTION The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at 3.3V. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Complimentary output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A Low-input level selects real-time data, and a High input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Data on the A or B bus, or both, can be stored in the internal flip-flops by Low-to-High transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay nAx to nBx or nBx to nAx Input capacitance Control pins I/O pin capacitance Total supply current CL = 50pF; VCC = 3.3V VI = 0V or 3.0V Outputs disabled; VI = 0V or 3.0V Outputs disabled; VCC = 3.6V CONDITIONS Tamb = 25°C TYPICAL 1.9 3 9 70 UNIT ns pF pF µA ORDERING INFORMATION PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74LVT16652A DL 74LVT16652A DGG NORTH AMERICA VT16652A DL VT16652A DGG DWG NUMBER SOT371-1 SOT364-1 LOGIC SYMBOL (IEEE/IEC) 56 1 55 54 2 3 EN1(BA) EN2(AB) C3 G4 C5 G6 52 29 28 30 31 27 26 EN7(BA) EN8(AB) C9 G10 C11 G12 42 5 w1 1 5D 6 4 4 3D 1 15 w1 7 11D 12 1 12 10 9D 10






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