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The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest.
Y Y Y Y
Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility Parallel loading independent of clock Dual clock inputs Fully static operation
3V to 15V 1V 0 45 VCC (typ ) fan out of 2 driving 74L
Y Y Y
Connection and Block Diagrams
Dual-In-Line Package
TL F 5897
– 2
Order Number MM54C165 or MM74C165
Please look into Section 8 Appendix D for availability of various package types
TL F 5897
– 1
Top View
TL F 5897
– 3
C1995 National Semiconductor Corporation
TL F 5897
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1)
If Military .
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