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74F190


Part Number 74F190
Manufacturer Fairchild
Title Up/Down Decade Counter
Description The ’F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array Address inputs are buffered to minimize loading and are fully decoded on...
Features Y Y Y Y Y TRI-STATE outputs for data bus applications Buffered inputs minimize loading Address decoding on-chip Diode clamped inputs minimize ringing Available in SOIC (300 mil only) Commercial 74F189PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual In Line 16...

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74F190 : The ’F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F190 to be used in programmable dividers The Count Enable input the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters In the counting modes state changes are initiated by the rising edge of the clock Features Y Y Y Y High-speed 125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Commercial 74F190PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Mo.

74F191 : The 74F191 is a 4-bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 - D3) is loaded into the counter and appears on the outputs when the Parallel Load (PL) input is Low. This operation overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of out.

74F191 : The 74F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 74F191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Features s High-Speed—125 MHz typical count frequency s Synchronous counting s Asynchronous parallel load s Cascadable Ordering Code: Order Number 74F191SC 74F191SJ 74F191PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-.

74F191 : The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters In the counting modes state changes are initiated by the rising edge of the clock Features Y Y Y Y High-Speed 125 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Commercial 74F191PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded .

74F192 : The 74F192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Features s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F192SJ 74F.

74F192 : The ’F192 is an up down BCD decade (8421) counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic thus simplifying multistage counter designs Individual preset inputs allow the circuit to be used as a programmable counter Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Features Y Guaranteed 4000V minimum ESD protection Commercial 74F192PC Military Package Number N1.

74F193 : The 74F193 is a 4-bit synchronous up/down counter in the binary mode. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the Low-to-High transition of either clock input. If the CPU clock is pulsed while CPD is held High, the device will count up. If CPD clock is pulsed while CPU is held High, the device will count down. The device can be cleared at any time by the asynchronous reset pin. It may also be loaded in parallel by activating the asynchronous parallel load pin. Inside the device are four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, asynchronous preset, load, and synchr.

74F193 : The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Ordering Code: Order Number 74F193SC 74F193SJ 74F193PC Package Number M16A .

74F193 : The ’F193 is an up down modulo-16 binary counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic thus simplifying multi-stage counter designs Individual preset inputs allow the circuit to be used as a programmable counter Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Features Y Guaranteed 4000V minimum ESD protection Commercial 74F193PC Military .

74F194 : The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0→Q1, etc.), or right to left (shift left, Q3→Q2, etc.), or parall.

74F194 : The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. Features s Typical shift frequency of 150 MHz s Asynchronous master reset s Hold (do nothing) mode s Fully synchronous serial or parallel data transfers Ordering Code: Order Number 74F194SC 74F194SJ 74F194PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ T.

74F194 : The ’F194 is a high-speed 4-bit bidirectional universal shift register As a high-speed multifunctional sequential building block it is useful in a wide variety of applications It may be used in serial-serial shift left shift right serial-parallel parallel-serial and parallel-parallel data register transfers The ’F194 is similar in operation to the ’F195 universal shift register with added features of shift left without external connections and hold (do nothing) modes of operation Features Y Y Y Y Typical shift frequency of 150 MHz Asynchronous master reset Hold (do nothing) mode Fully synchronous serial or parallel data transfers Commercial 74F194PC Military Package Number N16E Package.

74F195A : The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The 74F195A operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2→Q3 following each Low-to-High clock transition. The J and K inputs prov.

74F198 : The 74F198 Bidirectional Universal Shift Register is designed to incorporate virtually all of the features a system designer may want in a shift register. This circuit features parallel inputs and outputs, shift right and shift left serial inputs, operating mode select inputs, and direct overriding master reset input. The register has four distinct modes of operation: – Parallel (broadside) load – Shift right (in the direction Q0 toward Q7) – Shift left (in the direction Q7 toward Q0) – Inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the 8 bits of data and taking both mode control inputs, S0 and S1, High. The data is loaded into the associated flip-flop a.

74F199 : The 74F199 is an 8-bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. The device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel–to-serial data transfers at very high speeds. The 74F199 operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2 following each Low-to-High clock transition. The J and K inputs provide t.




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