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74F379 Datasheet PDF


Part Number 74F379
Manufacturer Fairchild
Title Quad Parallel Register
Description The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common...
Features the common Enable rather than common Master Reset. Features s Edge triggered D-type inputs s Buffered positive edge-triggered clock s Buffered common enable input s True and complement outputs Ordering Code: Order Number 74F379SC 74F379SJ 74F379PC Package Number M16A M16D N16E Package Description ...

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Datasheet 74F379 PDF File








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74F00 : 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F00N N74F00D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F00N I74F00D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Dna, Dnb Data inputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA Qn Data output 50/33 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. LOGIC DIAGRAM D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b 1 2 4 5 9 10 12 13 11 3 Q0 FUNCTION TABLE INPUTS Dna L L 8 Q2 OUTPUT Dnb L H L Qn H H H L 6 Q1 H Q3 SF00002 H H NOTES: H = High voltage level L = L.

74F00 : This device contains four independent gates, each of which performs the logic NAND function. Ordering Code: Order Number 74F00SC 74F00SJ 74F00PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An, Bn On Description HIGH/LOW Inputs Outputs 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −1 m.

74F00 : This device contains four independent gates, each of which performs the logic NAND function. Features n Guaranteed 4000V minimum ESD protection Ordering Code: Commercial 74F00PC See Section 0 Military Package Number N14A 54F00DM (Note 2) J14A M14A M14D 54F00FM (Note 2) 54F00LM (Note 2) W14B E20A 14-Lead (0.300" Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0.150" Wide) Molded Small Outline, JEDEC 14-Lead (0.300" Wide) Molded Small Outline, EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description DSXXX 74F00SC (Note 1) 74F00SJ (Note 1) Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with .

74F02 : 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F02N N74F02D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F02N I74F02D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb Qn Data inputs Data output DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. LOGIC DIAGRAM D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b 2 3 5 6 8 9 11 12 13 1 Q0 FUNCTION TABLE INPUTS Dna L L 10 Q2 OUTPUT Dnb L H L Qn H L L L 4 Q1 H Q3 SF00008 H H NOTES: 1 H = High voltage level 2 L.

74F02 : This device contains four independent gates, each of which performs the logic NOR function. Ordering Code: Order Number 74F02SC 74F02SJ 74F02PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An, Bn On Description HIGH/LOW Inputs Outputs 1.0/1.0 50/33.3 Input IIH/I IL Output I OH/IOL 20 µA/−0.6 mA −1 .

74F02 : This device contains four independent gates, each of which performs the logic NOR function. Ordering Code: Commercial 74F02PC See Section 0 Military Package Number N14A 54F02DM (Note 2) J14A M14A M14D 54F02FM (Note 2) 54F02LM (Note 2) W14B E20A 14-Lead (0.300" Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0.150" Wide) Molded Small Outline, JEDEC 14-Lead (0.300" Wide) Molded Small Outline, EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description DSXXX 74F02SC (Note 1) 74F02SJ (Note 1) Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix = DM.

74F04 : This device contains six independent gates, each of which performs the logic INVERT function. Features n Guaranteed 4000V minimum ESD protection Ordering Code: See Section 0 Commercial Military 74F04PC 74F04SC (Note 1) 74F04SJ (Note 1) 54F04DM (Note 2) 54F04FM (Note 2) 54F04LM (Note 2) Package Number N14A J14A M14A M14D W14B E20A Package Description 14-Lead (0.300" Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0.150" Wide) Molded Small Outline, JEDEC 14-Lead (0.300" Wide) Molded Small Outline, EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with en.

74F04 : 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F04N N74F04D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F04N I74F04D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS nA Data inputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA nY Data output 50/33 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. LOGIC DIAGRAM 1A 2A 3A 4A 5A VCC = Pin 14 GND = Pin 7 6A 1 3 5 9 11 13 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y FUNCTION TABLE INPUTS A L H NOTES: H = High voltage level L = Low voltage level OUTPUT Y H L SF00012 LOGIC SYMBOL 1 3 5 9 11 1.

74F04 : This device contains six independent gates, each of which performs the logic INVERT function. Ordering Code: Order Number 74F04SC 74F04SJ 74F04PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.L. Pin Names An On Description HIGH/LOW Inputs Outputs 1.0/1.0 50/33.3 Input IIH/I IL Output I OH/IOL 20 µA/−0.6 mA −1 mA.

74F06 : 14-pin plastic Dual In-line Package 14-pin plastic Small Outline COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F06N, N74F06AN N74F07D, N74F07AD PKG DWG # SOT27–1 SOT108–1 PIN CONFIGURATIONS 74F06/74F06A A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 74F07/74F07A 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 SF00016 SF00017 LOGIC SYMBOLS 74F06/74F06A 1 3 5 9 11 13 1 74F07/74F07A 3 5 9 11 13 A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4 A5 Y0 Y1 Y2 Y3 Y4 Y5 Y0 Y1 Y2 Y3 Y4 Y5 2 VCC = Pin 14 GND = Pin 7 4 6 8 10 12 VCC = Pin 14 GND = Pin 7 2 4 6 8 10 12 SF00018 SF00019 July 24, 1992 2 853–1122 07270 Philip.

74F06A : 14-pin plastic Dual In-line Package 14-pin plastic Small Outline COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F06N, N74F06AN N74F07D, N74F07AD PKG DWG # SOT27–1 SOT108–1 PIN CONFIGURATIONS 74F06/74F06A A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 74F07/74F07A 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 SF00016 SF00017 LOGIC SYMBOLS 74F06/74F06A 1 3 5 9 11 13 1 74F07/74F07A 3 5 9 11 13 A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4 A5 Y0 Y1 Y2 Y3 Y4 Y5 Y0 Y1 Y2 Y3 Y4 Y5 2 VCC = Pin 14 GND = Pin 7 4 6 8 10 12 VCC = Pin 14 GND = Pin 7 2 4 6 8 10 12 SF00018 SF00019 July 24, 1992 2 853–1122 07270 Philip.

74F07 : 14-pin plastic Dual In-line Package 14-pin plastic Small Outline COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F06N, N74F06AN N74F07D, N74F07AD PKG DWG # SOT27–1 SOT108–1 PIN CONFIGURATIONS 74F06/74F06A A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 74F07/74F07A 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 SF00016 SF00017 LOGIC SYMBOLS 74F06/74F06A 1 3 5 9 11 13 1 74F07/74F07A 3 5 9 11 13 A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4 A5 Y0 Y1 Y2 Y3 Y4 Y5 Y0 Y1 Y2 Y3 Y4 Y5 2 VCC = Pin 14 GND = Pin 7 4 6 8 10 12 VCC = Pin 14 GND = Pin 7 2 4 6 8 10 12 SF00018 SF00019 July 24, 1992 2 853–1122 07270 Philip.

74F07A : 14-pin plastic Dual In-line Package 14-pin plastic Small Outline COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F06N, N74F06AN N74F07D, N74F07AD PKG DWG # SOT27–1 SOT108–1 PIN CONFIGURATIONS 74F06/74F06A A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 A0 Y0 A1 Y1 A2 Y2 GND 1 2 3 4 5 6 7 74F07/74F07A 14 13 12 11 10 9 8 VCC A5 Y5 A4 Y4 A3 Y3 SF00016 SF00017 LOGIC SYMBOLS 74F06/74F06A 1 3 5 9 11 13 1 74F07/74F07A 3 5 9 11 13 A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4 A5 Y0 Y1 Y2 Y3 Y4 Y5 Y0 Y1 Y2 Y3 Y4 Y5 2 VCC = Pin 14 GND = Pin 7 4 6 8 10 12 VCC = Pin 14 GND = Pin 7 2 4 6 8 10 12 SF00018 SF00019 July 24, 1992 2 853–1122 07270 Philip.

74F08 : This device contains four independent gates, each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description 74F08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out Pin Names An, Bn On Description Inputs Outputs U.L. HIGH/LOW 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µ.

74F08 : This device contains four independent gates, each of which performs the logic AND function. Features n Guaranteed 4000V minimum ESD protection Ordering Code: Commercial 74F08PC See Section 0 Military Package Number N14A 54F08DM (Note 2) J14A M14A M14D 54F08FM (Note 2) 54F08LM (Note 2) W14B E20A 14-Lead (0.300" Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0.150" Wide) Molded Small Outline, JEDEC 14-Lead (0.300" Wide) Molded Small Outline, EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Package Description DSXXX 74F08SC (Note 1) 74F08SJ (Note 1) Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with e.

74F08 : 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5.0V ±10%, Tamb = 0°C to +70°C N74F08N N74F08D INDUSTRIAL RANGE VCC = 5.0V ±10%, Tamb = –40°C to +85°C I74F08N I74F08D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb Qn Data inputs Data output DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC DIAGRAM D0a D0b D1a D1b D2a D2b VCC = Pin 14 GND = Pin 7 D3a D3b 1 2 4 5 9 10 12 13 11 3 Q0 FUNCTION TABLE INPUTS Dna L L 8 Q2 OUTPUT Dnb L H L Qn L L L H 6 Q1 H Q3 SF00052 H H NOTES: H = High voltage level L.

74F10 : COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F10N, N74F11N N74F10D, N74F11D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Dna, Dnb, Dnc Qn Qn Data inputs Data output (74F10) Data output (74F11) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. PIN CONFIGURATIONS 74F10 D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2 D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7 74F11 14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2 SF00055 SF00056 LOGIC SYMBOLS 74F10 1 2 13 3 4 5 9 10 1.




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