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74F824 Datasheet PDF


Part Number 74F824
Manufacturer Philips
Title Bus interface registers
Description The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra dat...
Features flip-flops
• High speed parallel registers with positive edge-triggered D-type
• High performance bus interface buffering for wide data/address paths or busses carrying parity
• High impedance PNP base inputs for reduced loading (20µA in high and low states)
• IIL is 20µA vs 1000µA for AM29821 se...

File Size 140.22KB
Datasheet 74F824 PDF File








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74F821 : The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) .

74F821 : The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. Features s 3-STATE Outputs Ordering Code: Order Number 74F821SC 74F821SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009595 www.fairchildsemi.com 74F821 Unit Loading/Fan Out Pin Names D0–D9 OE CP O0–O9 Description Data Inputs Output Enable 3-STATE Inpu.

74F821 : The ’F821 is a 10-bit D-type flip-flop with TRI-STATE true outputs arranged in a broadside pinout The ’F821 is functionally and pin compatible with the AMD’s Am29821 Features Y Y TRI-STATE Outputs Direct replacement for AMD’s Am29821 Commercial 74F821SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F821SDM (Note 2) 74F821SC (Note 1) 54F821FM (Note 2) 54F821LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24F M24B W24C E28A Note 2 Military grade device with environmen.

74F822 : The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) .

74F823 : The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. Features s 3-STATE outputs s Clock Enable and Clear Ordering Code: Order Number 74F823SC 74F823SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009596 www.fairchildsemi.com 74F823 Unit Lo.

74F823 : The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) .

74F823 : The ’F823 is a 9-bit buffered register It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems The ’F823 is functionally and pin compatible with AMD’s Am29823 Features Y Y Y TRI-STATE outputs Clock Enable and Clear Direct replacement for AMD’s Am29823 Commercial 74F823SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Chip Carrier Type C 54F823SDM (Note 2) 74F823SC (Note 1) 54F823FM (Note 2) 54F823LM (Note 2) Note 1 Devices also available in 13 reel Use suf.

74F825 : The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. Features s 3-STATE output s Clock enable and clear s Multiple output enables Ordering Code: Order Number 74F825SC 74F825SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symb.

74F825 : The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) .

74F825 : The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Features Y Y Y Y TRI-STATE output Clock enable and clear Multiple output enables Direct replacement for AMD’s Am24825 Commercial 74F825SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carr.

74F826 : The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) .

74F827 : The 74F827 and 74F828 10-Bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (OE0, OE1) for maximum control flexibility. The 74F827 and 74F828 are functionally and pin compatible to AMD AM29827 and AM29828. The 74F828 is an inverting version of 74F827. TYPICAL PROPAGATION DELAY 6.0ns 6.0ns TYPICAL SUPPLY CURRENT (TOTAL) 60mA 55mA •IIL is 20µA vs FAST family spec of 600µA and 1000µA for AMD 29827/29828 series •Ideal where high speed, light bus loading and increased fan-in are required •Controlled rise and fall times to minimize ground bounce •Glitch free power-up in 3-State •Flow through pinout arch.

74F827 : The 74F827 and 74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The 74F828 is an inverting version of the 74F827. Features s 3-STATE output s 74F828 is inverting Ordering Code: Order Number 74F827SC 74F827SPC 74F828SC 74F828SPC Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDI.

74F827 : The ’F827 and ’F828 10-bit bus buffers provide high performance bus interface buffering for wide data address paths or buses carrying parity The 10-bit buffers have NOR output enables for maximum control flexibility The ’F827 and ’F828 are functionally- and pin-compatible to AMD’s Am29827 and Am29828 The ’F828 is an inverting version of the ’F827 Features Y Y Y TRI-STATE output ’F828 is inverting Direct replacement for AMD’s Am29827 and Am29828 Commercial 74F827SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chi.

74F828 : The 74F827 and 74F828 10-Bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (OE0, OE1) for maximum control flexibility. The 74F827 and 74F828 are functionally and pin compatible to AMD AM29827 and AM29828. The 74F828 is an inverting version of 74F827. TYPICAL PROPAGATION DELAY 6.0ns 6.0ns TYPICAL SUPPLY CURRENT (TOTAL) 60mA 55mA •IIL is 20µA vs FAST family spec of 600µA and 1000µA for AMD 29827/29828 series •Ideal where high speed, light bus loading and increased fan-in are required •Controlled rise and fall times to minimize ground bounce •Glitch free power-up in 3-State •Flow through pinout arch.

74F828 : The ’F827 and ’F828 10-bit bus buffers provide high performance bus interface buffering for wide data address paths or buses carrying parity The 10-bit buffers have NOR output enables for maximum control flexibility The ’F827 and ’F828 are functionally- and pin-compatible to AMD’s Am29827 and Am29828 The ’F828 is an inverting version of the ’F827 Features Y Y Y TRI-STATE output ’F828 is inverting Direct replacement for AMD’s Am29827 and Am29828 Commercial 74F827SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chi.




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