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74LS245C1 Datasheet PDF


Part Number 74LS245C1
Manufacturer SGS-Thomson
Title Octal Bus Transceiver
Description www.DataSheet4U.com DataSheet4U.com DataShee DataSheet4U.com www.DataSheet4U.com et4U.com DataSheet4U.com DataShee DataSheet4U.com www.Da...
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Datasheet 74LS245C1 PDF File








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74LS240 : SN74LS240 SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. http://onsemi.com • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address • Input Clamp Diodes Limit High-Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 3.0 – 15 IOL Output Current – Low 24 Unit V °C 20 Registers LOW POWER SCHO.

74LS240 : These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133Ω. Features s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at data inputs improves noise margins s Typical IOL (sink current) 24 mA s Typical IOH (source current) −15 mA s Typical propagation delay times Inverting Noninverting 10.5 ns 12 ns s Ty.

74LS240 : Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 20 11 1 10 5.5 0.80 Max 2.20 Max *0.22 ± 0.05 0.20 ± 0.04 0.20 7.80 + – 0.30 1.15 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 20 11 7.50 1 0.935 Max 10 2.65 Max *0.27 ± 0.05 0.25 ± 0.04 0.25 10.40 + – 0.40 1.45 0° – 8° 0.57 0..

74LS240 : These buffers line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers drivers employed as memory-address drivers clock drivers and bus-oriented transmitters receivers Featuring 400 mV of hysteresis at each low current PNP data line input they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133X Y Y Y Features Y Y Y Y Y TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at data inputs improves noise margins Typical IOL (sink current) 54LS 12 mA 74LS 24 mA Typical IOH (source current) b 12 mA 54LS b 15 mA 74LS Typical propagation delay times .

74LS240 : 54LS240/74LS240 LSTTL /(、) : • ; • PNP ; • 。 tpd=10ns Pd=130mW L L H A L H × Y H L Z Z= H= L= ×= : 、 。, ,,(400mV) 。 133Ω。 www.BDTIC.com BDTIC www.bdtic.com/Semiconductor Free Datasheet http://www.Datasheet4U.com 54LS240/74LS240 LSTTL /(、) Vcc VIH VIL IOH IOL TA 74Ⅱ 4.75 5 5.25 2.0 0.8 -15 24 -40 85 54 4.5 5 5.5 V 2.0 V 0.7 V -12 mA 12 mA -55 125 ℃ : (,) 74Ⅱ 54 -1.5 -1.5 V 0.2 0.4 0.2 0.4 V 2.4 2.0 0.35 0.5 0.1 20 -0.2 20 -20 -40 -225 27 44 50 -40 17 26 29 3.1 2.4 2.0 0.25 0.4 0.1 20 -0.2 20 -20 -225 27 44 50 3.1 V V V mA μA mA μA μA mA mA mA mA VIK Vcc= II=-18mA VT+-VT Vcc= Vcc= VIL= V =2V IOH=-3mA VOH IH Vcc= VIL=0.5V VIH=2V IOH= Vcc.

74LS241 : Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 20 11 1 10 5.5 0.80 Max 2.20 Max *0.22 ± 0.05 0.20 ± 0.04 0.20 7.80 + – 0.30 1.15 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 20 11 7.50 1 0.935 Max 10 2.65 Max *0.27 ± 0.05 0.25 ± 0.04 0.25 10.40 + – 0.40 1.45 0° – 8° 0.57 0..

74LS241 : These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133Ω. Features s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at data inputs improves noise margins s Typical IOL (sink current) 24 mA s Typical IOH (source current) −15 mA s Typical propagation delay times Inverting Noninverting 10.5 ns 12 ns s Ty.

74LS241 : These buffers line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers drivers employed as memory-address drivers clock drivers and bus-oriented transmitters receivers Featuring 400 mV of hysteresis at each low current PNP data line input they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133X Y Y Y Features Y Y Y Y Y TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at data inputs improves noise margins Typical IOL (sink current) 54LS 12 mA 74LS 24 mA Typical IOH (source current) b 12 mA 54LS b 15 mA 74LS Typical propagation delay times .

74LS241 : OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. SN54/74LS240 SN54/74LS241 SN54/74LS244 OCTAL BUFFER/ LINE DRIVER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Input Clamp Diodes Limit High-Speed Termination Effects LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN54 / 74LS240 VCC 2G 20 19 1Y1 18 2A4 1Y2 17 16 2A3 15 1Y3 2A2 1Y4 14 13 12 2A1 11 20 1 J SUFFIX CERAMIC CASE 7.

74LS243 : This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. Features s Two-way asynchronous communication between data buses s PNP inputs reduce DC loading on bus line s Hysteresis at data inputs improves noise margin Ordering Code: Order Number DM74LS243M DM74LS243N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Tab.

74LS244 : .

74LS244 : These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133Ω. Features s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at data inputs improves noise margins s Typical IOL (sink current) 24 mA s Typical IOH (source current) −15 mA s Typical propagation delay times Inverting Noninverting 10.5 ns 12 ns 18 ns.

74LS244 : Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 20 11 1 10 5.5 0.80 Max 2.20 Max *0.22 ± 0.05 0.20 ± 0.04 0.20 7.80 + – 0.30 1.15 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 20 11 7.50 1 0.935 Max 10 2.65 Max *0.27 ± 0.05 0.25 ± 0.04 0.25 10.40 + – 0.40 1.45 0° – 8° 0.57 0..

74LS244 : SN74LS240 SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. http://onsemi.com • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address • Input Clamp Diodes Limit High-Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 3.0 – 15 IOL Output Current – Low 24 Unit V °C 20 Registers LOW POWER SCHO.

74LS245 : SN74LS245 Octal Bus Transceiver The SN74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input (DR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input (E) can be used to isolate the buses. http://onsemi.com • • • • Hysteresis Inputs to Improve Noise Immunity 2-Way Asynchronous Data Bus Communication Input Diodes Limit High-Speed Termination Effects ESD 3500 Volts LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) VCC 20 E 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 LOW POWER SCHOTTKY 20 1 1 DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9.

74LS245 : These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A Bus to the B Bus or from the B Bus to the A Bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated. Features s Bi-Directional bus transceiver in a high-density 20-pin package s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at bus inputs improve noise margins s Typical propagation delay times, port-to-port .

74LS245 : These octal bus transceivers are designed for asynchronous two-way communication between data buses The control function implementation minimizes external timing requirements The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input The enable input (G) can be used to disable the device so that the buses are effectively isolated Y Y Y Y Y Y Features Y Y Y Bi-Directional bus transceiver in a high-density 20-pin package TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at bus inputs improve noise margins Typical propagation delay times port.




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