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NT5DS64M4BF Datasheet PDF


Part Number NT5DS64M4BF
Manufacturer Nanya Techology
Title (NT5DSxxMxBx) 256Mb DDR SDRAM
Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRA...
Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166













• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at...

File Size 1.36MB
Datasheet NT5DS64M4BF PDF File








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NT5DS64M4BF : The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle An auto .

NT5DS64M4BG : The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle DataShee.

NT5DS64M4BS : The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle DataShee.

NT5DS64M4BT : The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle DataShee.

NT5DS64M4BW : The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate As with standard SDRAMs, the pipelined, multibank architecDataSheet4U.com DataShee architecture is essentially a 2n prefetch architecture with an ture of DDR SDRAMs allows for concurrent operation, interface designed.




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