HYB39S256800 Datasheet

HYB39S256800 (HYB39S256xxx) 256 MBit Synchronous DRAM

HYB 39S256400T-8B on request HYB 39S256400T-10 on request HYB 39S256800T-8 on request HYB 39S256800T-8B on request HYB 39S256800T-10 on request HYB 39S256800T-8 www.DataSheet4U.com on request HYB 39S256800T-8B on request HYB 39S256800T-10 on request Pin Description and Pinouts CLK CKE CS RAS C.

Features

st Length: 1, 2, 4, 8 The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as 4 banks × 16 MBit × 4, 4 banks × 8 MBit × 8 and 4 banks × 4 MBit × 16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of t.