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ML145158 Datasheet PDF


Part Number ML145158
Manufacturer LANSDALE Semiconductor
Title (ML145151 - ML145158) Parallel-Input PLL Frequency Synthesizer Interfaces
Description INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled int...
Features consist of a reference oscillator, selectable
  –reference divider, digital
  –phase detector, and 14
  –bit programmable divide
  –by
  –N counter.
• Operating Temperature Range: TA =
  – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On
  – or Off
  –Chip Reference Oscill...

File Size 1.57MB
Datasheet ML145158 PDF File








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ML145027 : section. Page 3 of 19 www.lansdale.com Issue 0 ML145026, ML145027, ML145028 www.DataSheet4U.com LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS — ML145026 *, ML145027, and ML145028 (Voltage Referenced to VSS) Guaranteed Limit VDD V (Vin = VDD or 0) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 15 – 40°C Min — — — 4.95 9.95 14.95 — — — 3.5 7.0 11 – 2.5 – 0.52 – 1.3 – 3.6 0.52 1.3 3.6 — — — — Max 0.05 0.05 0.05 — — — 1.5 3.0 4.0 — — — — — — — — — — — — — ± 0.3 Min — — — 4.95 9.95 14.95 — — — 3.5 7.0 11 – 2.1 – 0.44 – 1.1 – 3.0 0.44 1.1 3.0 3.0 16 35 — 25°C Max 0.05 0.05 0.05 — — — 1.5 3.0 4.0 — — — — — — — — — — 11 60 120 ± 0.3 Min — — — 4.95 9.95 14..

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ML145040 : DIGITAL INPUTS AND OUTPUTS CS (Pin 15) Active–low chip select input. CS provides three–state control of Dout. CS at a high logic level forces Dout to a high–impedance state. IN addition, the device recognizes the falling edge of CS as a serial interface reset to provide synchronization between the MPU and the A/D converter’s serial data stream. To prevent a spurious reset from occurring due to noise on the CS input, a delay circuit has been included such that a CS signal of duration ≤1 A/D CLK period (ML145040) or ≤500 ns (ML145041) is ignored. A valid CS signal is acknowledged when the duration is ≥3 A/D CLK periods (ML145040) or ≥3 µs (ML145041) CAUTION A reset aborts a conversion sequen.

ML145041 : DIGITAL INPUTS AND OUTPUTS CS (Pin 15) Active–low chip select input. CS provides three–state control of Dout. CS at a high logic level forces Dout to a high–impedance state. IN addition, the device recognizes the falling edge of CS as a serial interface reset to provide synchronization between the MPU and the A/D converter’s serial data stream. To prevent a spurious reset from occurring due to noise on the CS input, a delay circuit has been included such that a CS signal of duration ≤1 A/D CLK period (ML145040) or ≤500 ns (ML145041) is ignored. A valid CS signal is acknowledged when the duration is ≥3 A/D CLK periods (ML145040) or ≥3 µs (ML145041) CAUTION A reset aborts a conversion sequen.

ML145050 : . Page 2 of 15 www.lansdale.com Issue B ML145050, ML145051 www.DataSheet4U.com LANSDALE Semiconductor, Inc. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated) Symbol VIH VIL VOH VOL Iin IOZ IDD Iref IAl Parameter Minimum High-Level Input Voltage (Din, SCLK, CS, ADCLK) Maximum Low-Level Input Voltage (Din, SCLK, CS, ADCLK) Minimum High-Level Output Voltage (Dout, EOC) Minimum Low-Level Output Voltage (Dout, EOC) Maximum Input Leakage Current (Din, SCLK, CS, ADCLK) Maximum Three-State Leakage Current (Dout) Maximum Power Supply Current Maximum Static Analog Reference Current (Vref) Maximum.

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ML145053 : . DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated) Symbol VIH VIL VOH VOL Iin IOZ IDD Iref IAl Parameter Minimum High-Level Input Voltage (Din, SCLK, CS) Maximum Low-Level Input Voltage (Din, SCLK, CS) Minimum High-Level Output Voltage (Dout, EOC) Minimum Low-Level Output Voltage (Dout, EOC) Maximum Input Leakage Current (Din, SCLK, CS) Maximum Three-State Leakage Current (Dout) Maximum Power Supply Current Maximum Static Analog Reference Current (Vref) Maximum Analog Mux Input Leakage Current between all deselected inputs and any selected input (AN0–AN4) Iout = – 1.6 mA Iout = – 20 µA Iout.

ML145106 : P0 – P8 Programmable Inputs (PDIP – Pins 17 – 9; SOG – Pins 19, 17 – 14, 12 – 9) Programmable divider inputs (binary). fin Frequency Input (PDIP, SOG – Pin 2) Frequency input to programmable divider (derived fromVCO). OSCin, OSCout Oscillator Input and Oscillator Output (PDIP, SOG – Pins 3, 4) Oscillator/amplifier input and output terminals. Page 4 of 8 www.lansdale.com Issue b ML145106 www.DataSheet4U.com LANSDALE Semiconductor, Inc. Legacy Applications Information PLL SYNTHESIZER APPLICATIONS The ML145106 is well suited for applications in CB radios because of the channelized frequency requirements. A typical 40 channel CB transceiver synthesizer, using a single crystal reference, i.

ML145145 : INPUT PINS D0 – D3 Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 is most signigicant bit. f in Frequency Input (PDIP – Pin 3, SOG – Pin 4) Input to ÷N portion of synthesizer. f in is typically derived from the loop VCO and is ac couples. For larger amplitude signals (standard CMOS – logic levels) dc coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG – Pins 7, 8) These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate val.

ML145146 : INPUT PINS D0 - D3 Data Inputs (Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 (Pin 19) is the most significant bit. f in Frequency Input (Pin 3) Input to ÷N portion of synthesizer f in is typically derived from loop VCO and is AC coupled into Pin 3. For larger amplitude signals (standard CMOS – logic levels) DC coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (Pins 7 and 8) These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout t.

ML145151 : INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels) DC coupling may be used. RA0 – RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code RA2 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 .

ML145152 : INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels) DC coupling may be used. RA0 – RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code RA2 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 .

ML145155 : INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels) DC coupling may be used. RA0 – RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code RA2 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 .

ML145156 : INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels) DC coupling may be used. RA0 – RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code RA2 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 .

ML145157 : INPUT PINS f in Frequency Input (Pin 1) Input to the ÷N portion of the synthesizer. f in is typically derived from loop VCO and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels) DC coupling may be used. RA0 – RA2 Reference Address Inputs (Pins 5, 6, 7) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter data to the zero state. Reference Address Code RA2 0 0 0 0 1 1 1 1 RA1 0 0 1 1 0 0 1 1 RA0 0 1 0 1 0 1 0 1 Total Divide Value 8 128 256 512 1024 2048 2410 .




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