4014BT Datasheet

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4014BT Datasheet - HEF4014B

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Datasheet: 4014BT datasheet

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Description: HEF4014B 8-bit static shift register Rev . 9 — 21 March 2016 Product data she et 1. General description The HEF4014 B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7) , a synchronous serial data input (DS), a synchronous parallel enable input (P E), a LOW-to-HIGH edge-triggered clock input (CP) and buffered parallel output s from the last three stages (Q5 to Q7) . Operation is synchronous and the devi ce is edge-triggered on the LOW-to-HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop t ype. When PE is HIGH, data is loaded in to the register from D0 to D7 on the LO W-to-HIGH transition of CP. When PE is

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