DatasheetsPDF.com

4042B Datasheet

Part Number 4042B
Manufacturers NXP
Logo NXP
Description Quadruple D-latch
Datasheet 4042B Datasheet4042B Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4042B MSI Quadruple D-latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple D-latch DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), fo.

  4042B   4042B






Part Number 4042B
Manufacturers R & E International
Logo R & E International
Description CMOS QUAD LATCH
Datasheet 4042B Datasheet4042B Datasheet (PDF)

www.DataSheet4U.com .

  4042B   4042B







Quadruple D-latch

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4042B MSI Quadruple D-latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple D-latch DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 as long as both E0 and E1 remain in the same state. When E0 and E1 are different, D0 to D3 do not affect O0 to O3 and the information in the latch is stored. O0 to O3 are always the complement of O0 to O3. The exclusive-OR input structure allows the choice of either polarity for E0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. HEF4042B MSI Fig.2 Pinning diagram. HEF4042BP(N): HEF4042BD(F): HEF4042BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D0 to D3 E0 and E1 O0 to O3 O0 to O3 data inputs enable inputs parallel latch outputs complementary parallel latch .


2005-03-30 : M27C320    M27C322    M27C400    M27C405    M27C512    2SD600    2SD600K    2SD601A    2SD602    2SD602A   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)