54AC11010

Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = A S B S C or Y = A + B + C in positive logic. The 54AC11010 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11010 is characterized for operation from – 40°C to 85°C. 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCLS057 – MAY 1987 – REVISED APRIL 1993 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE (TOP VIEW) 1A 1Y 2Y GND GND 3Y 3C 3B 1 2 3 4 5 6 7 8 16 1B 15 1C 14 2A 13 VCC 12 VCC 11 2B 10 2C 9 3A 54AC11010 . . . FK PACKAGE (TOP VIEW) 2A VCC NC VCC 2B 3 2 1 20 19 1C 4 18 2C 1B 5 17 3A NC 6 16 NC 1A 7 15 3B 1Y 8 14 3C 9 10 11 12 13 2Y GND NC GND 3Y NC – No internal connection FUNCTION TABLE (each gate) INPUTS ABC OUTPUT Y HHH L LXX H XLX H XXL H EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all par...