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54AC11109
Dual J-K Positive-edge-Triggered Flip-Flops
Description
ăą 54AC11109, 74AC11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCAS450 − MARCH 1987 − REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
CMOS
) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C...
Texas Instruments
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