ą 54AC11238, 74AC11238 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS ą
SCAS039A − APRIL 1988 − REVISED APRIL 1993
• Designed...
ą 54AC11238, 74AC11238 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS ą
SCAS039A − APRIL 1988 − REVISED APRIL 1993
Designed Specifically for High-Speed
54AC11238 . . . J PACKAGE
Memory Decoders and Data Transmission
74AC11238 . . . D OR N PACKAGE
Systems
(TOP VIEW)
Noninverting Version of ′AC11138 Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
Y1 Y2 Y3 GND Y4 Y5 Y6 Y7
1 2 3 4 5 6 7 8
16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A 9 G2B
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
54AC11238 . . . FK PACKAGE
Package Options Include Plastic
(TOP VIEW)
B C NC VCC G1
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
3 2 1 20 19
A4
18 G2A
description
Y0 5
17 G2B
The ′AC11238 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short
NC 6
16 NC
Y1 7
15 Y7
Y2 8
14 Y6
9 10 11 12 13
propagation delay times. In high-performance
Y3 GND
NC Y4 Y5
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
NC − No internal connection
fast enable circuit, the delay times of this decoder
and the enable time of the memory are usually less than the typical access time of the mem...
