• 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
• Flow-Through Architecture Optimizes
PCB Layout
• ...
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
t EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic Small-
Outline Packages, Plastic Shrink Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
This octal buffer or line driver is designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the AC11240 and AC11244, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical G (activelow output control) inputs, and complementary G and G inputs. This device features a high fan-out.
The 54AC11241 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11241 is characterized for operation from – 40°C to 85°C.
54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS032A – JULY 1987 – REVISED APRIL 1993
54AC11241 . . . JT PACKAGE 74AC11241 . . . DB, DW OR NT PACKAGE
(TOP VIEW)
1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4
1 2 3 4 5 6 7 8 9 10 11 12
24 1G
23 1A1
22 1A2
21 1A3
20 1A4 19 VCC 18 VCC 17 2A1 16 2A2 15 2A3 14 2A4 13 2G
54AC11241 . . . FK PACKAGE (TOP VIEW)
1A...