54AC16244, 74AC16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS120A – MARCH 1990 – REVISED APRIL 1996
D Memb...
54AC16244, 74AC16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS120A – MARCH 1990 – REVISED APRIL 1996
D Members of the Texas Instruments
Widebust Family
D 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D Flow-Through Architecture Optimizes PCB
Layout
D Distributed VCC and GND Configuration
Minimizes High-Speed Switching Noise
D EPIC t (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
description
The ’AC16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
54AC16244 . . . WD PACKAGE 74AC16244 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 2OE 47 1A1 ...