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54LS190 COUNTERS Datasheet PDF

SYNCHRONOUS UP/DOWN COUNTERS

SYNCHRONOUS UP/DOWN COUNTERS

 

 

 

Part Number 54LS190
Description SYNCHRONOUS UP/DOWN COUNTERS
Feature SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/ UP MODE CONTROL SDLS072 – DECEMBER 19 72 – REVISED MARCH 1988 PRODUCTION D ATA information is current as of public ation date.
Products conform to specifi cations per the terms of Texas Instrume nts standard warranty.
Production proce ssing does not necessarily include test ing of all parameters.

• POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyrig ht © 1988, Texas Instruments Incorpora ted 1 SN54190, SN54191, SN54LS190, SN5 4LS191, SN74190, SN74191, SN74LS190, SN 74LS191 SYNCHRONOUS U .
Manufacture Texas Instruments
Datasheet
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54LS190

 

 

 


 

 

 

Part Number 54LS190
Description PRESETTABLE BCD/DECADE UP/DOWN COUNTERS
Feature PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTE RS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter.
State c hanges of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Para llel Load (PL) input overrides counting and loads the data present on the Pn i nputs into the flip-flops, which makes it possible to use the circuits as prog rammable counters.
A Count Enable (CE) input serves as the carry / borrow inpu t in multi-sta .
Manufacture Motorola
Datasheet
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54LS190

 

 

 


 

 

 

Part Number 54LS190
Description Synchronous 4-Bit Up/Down Counters
Feature DM54LS190 DM74LS190 DM54LS191 DM74LS191 Synchronous 4-Bit Up Down Counters with Mode Control May 1989 DM54LS190 DM74 LS190 DM54LS191 DM74LS191 Synchronous 4 -Bit Up Down Counters with Mode Control General Description These circuits are synchronous reversible up down counter s The LS191 is a 4-bit binary counter a nd the LS190 is a BCD counter Synchrono us operation is provided by having all flip-flops clocked simultaneously so th at the outputs change simultaneously wh en so instructed by the steering logic This mode of operation eliminates the o utput counting spikes normally associat ed with asynch .
Manufacture National Semiconductor
Datasheet
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54LS190

 

 

 

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