56F802

DSP56F802/D Rev. 4.0, 08/2003 56F802 Technical Data 56F802 16-bit Hybrid Controller Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes Hardware DO and REP loops 6-channel PWM Module with fault input Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel) Serial Communications Interface (SCI) 8K × 16-bit words Program Flash 1K × 16-bit words Program RAM 2K × 16-bit words Data Flash 1K × 16-bit words Data RAM 2K × 16-bit words Boot Flash Two General Purpose Quad Timers with 2 external outputs JTAG/OnCETM port for debugging 4 shared GPIO On-chip relaxation oscillator 32-pin LQFP Package PWM Outputs 6 Fault A0 2 A/D1 3 A/D2 ADC VREF PWMA RESET 5 JTAG/ OnCE Port VCAPC VDD 22 VSS* VDDA...