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5962-8688001QA Datasheet

Part Number 5962-8688001QA
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS ARINC Bus Interface Circuit
Datasheet 5962-8688001QA Datasheet5962-8688001QA Datasheet (PDF)

HS-3282 REFERENCE AN400 March 1997 CMOS ARINC Bus Interface Circuit Description Features • ARlNC Specification 429 Compatible The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC • Data Rates of 100 Kilobits or 12.5 Kilobits Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with • Separate Receiver and Transmitter Section the HS-3182, a monolithic Dl bipolar differential l.

  5962-8688001QA   5962-8688001QA






CMOS ARINC Bus Interface Circuit

HS-3282 REFERENCE AN400 March 1997 CMOS ARINC Bus Interface Circuit Description Features • ARlNC Specification 429 Compatible The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC • Data Rates of 100 Kilobits or 12.5 Kilobits Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with • Separate Receiver and Transmitter Section the HS-3182, a monolithic Dl bipolar differential line driver • Dual and Independent Receivers, Connecting Directly designed to meet the specifications of ARINC 429. The to ARINC Bus ARINC 429 bus interface circuit consists of two (2) receivers and a transmitter operating independently as shown in • Serial to Parallel Receiver Data Conversion Figure 1. The two receivers operate at a frequency that is ten • Parallel to Serial Transmitter Data Conversion (10) times the receiver data rate, which can be the same or different from the transmitter data rate. Although the two • Word Lengths of 25 or 32 Bits receivers operate at the same frequency, they are • Parity Status of Received Data functionally independent and each receives serial data asynchronously. The transmitter section of the ARINC bus • Generate Parity of Transmitter Data interface circuit consists mainly of a First-In First-Out (FIFO) • Automatic Word Gap Timer memory and timing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for transmission serially. .


2007-04-25 : 908E425    AD1990    TS2418    TS2411    5962-8688001QA    5962-8688001XA    M1S18TAJ    M1S1xxxx    M1S2xxxx    M1S3xxxx   


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