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66AK2E05 Datasheet

Part Number 66AK2E05
Manufacturers Texas Instruments
Logo Texas Instruments
Description SoC
Datasheet 66AK2E05 Datasheet66AK2E05 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 66AK2E0x Features and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Ins.

  66AK2E05   66AK2E05






Part Number 66AK2E02
Manufacturers Texas Instruments
Logo Texas Instruments
Description SoC
Datasheet 66AK2E05 Datasheet66AK2E02 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 66AK2E0x Features and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Ins.

  66AK2E05   66AK2E05







SoC

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community 66AK2E05, 66AK2E02 SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1 66AK2E0x Features and Description 1.1 Features 1 • ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Instruction and Data Caches per Core – AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3 • One TMS320C66x DSP Core Subsystem (C66x CorePacs), Each With – 1.4 GHz C66x Fixed/Floating-Point DSP Core • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz • 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory • 32K Byte L1P Per CorePac • 32K Byte L1D Per CorePac • 512K Byte Local L2 Per CorePac • Multicore Shared Memory Controller (MSMC) – 2 MB SRAM Memory Shared by DSP CorePacs and ARM CorePac – Memory Protection Unit for Both SRAM and DDR3_EMIF • Multicore Navigator – 8k Multi-Purpose Hardware Queues with Queue Manager – One Packet-Based DMA Engine for ZeroOverhead Transfers • Network Coprocessor – Packet Accelerator Enables Support for • Transport Plane IPsec, GTP-U, SCTP, PDCP • L2 User Plane PDCP (RoHC, Air Ciphering) • 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second – Security Accelerator Eng.


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