70V08L

HIGH-SPEED 3.3V 64K x 8 DUAL-PORT STATIC RAM 70V08L Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT70V08L Active: 550mW (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT70V08 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ LVTTL-compatible, single 3.3V (±0.3V) power supply ◆ Available in a 100-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Functional Block Diagram R/W L CE0L CE1L OEL R/WR CE0R CE1R OE R I/O 0-7L I/O Control I/O Control BUSY (1,2) L A15L A0L Address Decoder 64Kx8 MEMORY ARRAY 70V08 A15L A 0L CE 0L CE1L OE L R/W L ARBITRATION INTERRUPT SEMAPHORE LOGIC SEM L INT (2) L (1) M/S NOTES: 1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). 1 I/O 0-7R BUSY (1,2) R Address Decoder A15R A 0R A15R A 0R CE0R CE1R OER R/WR 3740 drw 01 SE...