7143SA

HIGH SPEED 2K X 16 DUAL-PORT SRAM 7133SA/LA 7143SA/LA Features ◆ High-speed access – Military: 35/55/70/90ns (max.) – Industrial: 25ns (max.) – Commercial: 20/25/35/45/55/70/90ns (max.) ◆ Low-power operation – IDT7133/43SA Active: 1150mW (typ.) Standby: 5mW (typ.) – IDT7133/43LA Active: 1050mW (typ.) Standby: 1mW (typ.) ◆ Versatile control for write: separate write control for lower and upper byte of each port Functional Block Diagram R/WLUB CEL ◆ MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 ◆ On-chip port arbitration logic (IDT7133 only) ◆ BUSY output flag on IDT7133; BUSY input on IDT7143 ◆ Fully asynchronous operation from either port ◆ Battery backup operation–2V data retention ◆ TTL-compatible; single 5V (±10%) power supply ◆ Available in 68-pin ceramic PGA, Flatpack, PLCC and 100- pin TQFP ◆ Military product compliant to MIL-PRF-38535 QML ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information R/WRUB CER R/WLLB OEL R/WRLB OER I/O8L - I/O15L I/O0L - I/O7L BUSYL(1) A10L A0L I/O CONTROL I/O CONTROL ADDRESS DECODER 11 CEL MEMORY ARRAY ARBITRATION LOGIC (IDT7133 ONLY) ADDRESS DECODER 11 CER NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. I/O8R - I/O15R I/O0R - I/O7R BUSYR(1) A10R A0R 2746 drw 01 ©2019 Integrated Device Technology, Inc. 1 AUGUST 2019 DSC 2746/16 7133SA/LA, 7143SA/...