74173

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 3-State D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC74HC173 is identical in pinout to the LS173. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data, when enabled, are clocked into the four D flip–flops with the rising edge of the common Clock. When either or both of the Output Enable Controls is high, the outputs are in a high–impedance state. This feature allows the HC173 to be used in bus–oriented systems. The Reset feature is asynchronous and active high. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity 208 FETs or 52 Equivalent Gates LOGIC DIAGRAM D0 14 D1 13 D2 12 D3 11 3 Q0 4 Q1 5 Q2 6 Q3 16 MC74HC173 N SUFFIX PLASTIC PACKAGE CASE 648–08 1 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING INFORMATION MC74HCXXXN MC74HCXXXD Plastic SOIC PIN ASSIGNMENT OE1 OE2 Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET D0 D1 D2 D3 DE2 DE1 DATA INPUTS 3–STATE NONINVERTING OUTPUTS Q1 Q2 Q3 CLOCK CLOCK 7 DE1 9 DE2 10 RESET 15 OUTPUT ENABLES OE1 1 2 OE2 VCC = PIN 16 GND = PIN 8 GND DATA– ENABLES FUNCTION TABLE Inputs Output Enables OE1 L L L L L L L L L H H OE2 L L L L L L...