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7474 Datasheet

Part Number 7474
Manufacturers Fairchild
Logo Fairchild
Description Dual Positive-Edge-Triggered D-Type Flip-Flops
Datasheet 7474 Datasheet7474 Datasheet (PDF)

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a volt.

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Part Number 7474
Manufacturers Texas Instruments
Logo Texas Instruments
Description Dual D-Type Positive-Edge-Triggered Flip-Flops
Datasheet 7474 Datasheet7474 Datasheet (PDF)

SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  1988, Texas Instruments Incorporated 1 SN5.

  7474   7474







Dual Positive-Edge-Triggered D-Type Flip-Flops

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM7474M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow DM7474N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q LHXXHL HLXXLH L L XXHH (Note 1) (Note 1) HH ↑ HH L HH↑ L LH H H L X Q0 Q0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level ↑ = Positive-going transition of .


2005-06-10 : 7474    R6522    2SK3296    GL7912    BC264    BC264    IN4749A    MC6800    MC6809    MC68060   


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