Generator. 74ACT715-R Datasheet

74ACT715-R Datasheet PDF

Part 74ACT715-R
Description Programmable Video Sync Generator
Feature 74ACT715•74ACT715-R Programmable Video Sync Generator www.DataSheet4U.com November 1988 Revised De.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACT715-R Datasheet





74ACT715-R
www.DataSheet4U.com
November 1988
Revised December 1998
74ACT715•74ACT715-R
Programmable Video Sync Generator
General Description
The ACT715 and ACT715-R are 20-pin TTL-input compati-
ble devices capable of generating Horizontal, Vertical and
Composite Sync and Blank signals for televisions and
monitors. All pulse widths are completely definable by the
user. The devices are capable of generating signals for
both interlaced and noninterlaced modes of operation.
Equalization and serration pulses can be introduced into
the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the sys-
tem architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all respects
except that the ACT715-R is mask programmed to default
to a Clock Enabled state. Bit 10 of the Status Register
defaults to a logic “1”. Although completely (re)programma-
ble, the ACT715-R version is better suited for applications
using the default 14.31818 MHz RS-170 register values.
This feature allows power-up directly into operation, follow-
ing a single CLEAR pulse.
Features
s Maximum Input Clock Frequency > 130 MHz
s Interlaced and non-interlaced formats available
s Separate or composite horizontal and vertical Sync and
Blank signals available
s Complete control of pulse width via register
programming
s All inputs are TTL compatible
s 8 mA drive on all outputs
s Default RS170/NTSC values mask programmed into
registers
s ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818 MHz
RS170 timing
Ordering Code:
Order Number Package Number
Package Description
74ACT715SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT715-RSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715-RPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP and SOIC
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010137.prf
www.fairchildsemi.com



74ACT715-R
Logic Block Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the
ACT715.
Data Inputs D0–D7: The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA signal is latched into the
device on the falling edge of the LOAD signal. The signal
determines if an address (0) or data (1) is present on the
data bus.
L/HBYTE: The L/HBYTE signal is latched into the device
on the falling edge of the LOAD signal. The signal deter-
mines if data will be read into the 8 LSB’s (0) or the 4
MSB’s (1) of the Data Registers. A 1 on this pin when an
ADDR/DATA is a 0 enables Auto-Load Mode.
LOAD: The LOAD control pin loads data into the Address
or Data Registers on the rising edge. ADDR/DATA and L/
HBYTE data is loaded into the device on the falling edge of
the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.
CLOCK: System CLOCK input from which all timing is
derived. The clock pin has been implemented as a Schmitt
trigger for better noise immunity. The CLOCK and the
LOAD signal are asynchronous and independent. Output
state changes occur on the falling edge of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initial-
izes the device when it is HIGH. Initialization consists of
setting all registers to their mask programmed values, and
initializing all counters, comparators and registers. The
CLEAR pin has been implemented as a Schmitt trigger for
better noise immunity. A CLEAR pulse should be asserted
by the user immediately after power-up to ensure proper
initialization of the registers—even if the user plans to
(re)program the device.
Note: A CLEAR pulse will disable the CLOCK on the ACT715 and will
enable the CLOCK on the ACT715-R.
ODD/EVEN: Output that identifies if display is in odd
(HIGH) or even (LOW) field of interlace when device is in
interlaced mode of operation. In noninterlaced mode of
operation this output is always HIGH. Data can be serially
scanned out on this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal
based on value of the Status Register. Equalization and
Serration pulses will (if enabled) be output on the VCSYNC
signal in composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking signal, Horizontal
Gating signal or Cursor Position based on value of the Sta-
tus Register.
HSYNVDR: Outputs Horizontal Sync signal, Vertical Gat-
ing signal or Vertical Interrupt signal based on value of Sta-
tus Register.
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