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74AHC74-Q100 Datasheet

Part Number 74AHC74-Q100
Manufacturers nexperia
Logo nexperia
Description Dual D-type flip-flop
Datasheet 74AHC74-Q100 Datasheet74AHC74-Q100 Datasheet (PDF)

74AHC74-Q100; 74AHCT74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 3 — 22 April 2020 Product data sheet 1. General description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) a.

  74AHC74-Q100   74AHC74-Q100






Dual D-type flip-flop

74AHC74-Q100; 74AHCT74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 3 — 22 April 2020 Product data sheet 1. General description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC74-Q100: CMOS level • For 74AHCT74-Q100: TTL.


2019-07-26 : PN2904A    PN2905A    BZX384    BZX384-B3V3    BZX384-C24    BZX384-C20    BZX384-C22    BZX384-C27    BZX384-C30    BZX384-C33   


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