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74AHCT00 gate Datasheet PDFQuad 2-input NAND gate Quad 2-input NAND gate |
| Part Number | 74AHCT00 |
|---|---|
| Description | Quad 2-input NAND gate |
| Feature | INTEGRATED CIRCUITS
DATA SHEET
74AHC00 ; 74AHCT00 Quad 2-input NAND gate
Produ ct specification Supersedes data of 19 98 Dec 09 File under Integrated Circuit s, IC06 1999 Sep 23
Philips Semiconduc tors
Product specification
Quad 2-in put NAND gate
FEATURES • ESD protecti on: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CD M EIA/JESD22-C101 exceeds 1000 V • Ba lanced propagation delays • All input s have Schmitt-trigger actions • Inpu ts accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified . |
| Manufacture | NXP |
| Datasheet |
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| Part Number | 74AHCT00 |
|---|---|
| Description | QUADRUPLE 2-INPUT NAND GATES |
| Feature | NEW PRODUCT
74AHCT00
QUADRUPLE 2-INPUT NAND GATES
Description
The 74AHCT00 pr ovides provides four independent 2-inpu t NAND gates with standard push-pull ou tputs. The device is designed for opera tion with a power supply range of 4. 5V to 5. 5V. The gates perform the Boolean function: Pin Assignments Y = A • B or Y = A + B Features • Wide Supply Voltage Range from 4. 5V to 5. 5V • In puts Are TTL Voltage Level Compatible Outputs Sink or Source 8mA at VCC = 4. 5V • CMOS Low Power Consumption • Schmitt Trigger Action at All Inputs ESD Protection Exceeds JESD 22 20 0-V Machine Model (A115-A) . |
| Manufacture | Diodes |
| Datasheet |
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| Part Number | 74AHCT00 |
|---|---|
| Description | Quad 2-input NAND gate |
| Feature | 74AHC00; 74AHCT00
Quad 2-input NAND gate
Rev. 5 — 26 May 2020 Product data s heet 1. General description The 74AHC0 0; 74AHCT00 are quad 2-input NAND gates . Inputs are overvoltage tolerant. This feature allows the use of these device s as translators in mixed voltage envir onments. 2. Features • Wide supply voltage range from 2. 0 V to 5. 5 V • I nput levels: • For 74AHC00: CMOS leve l • For 74AHCT00: TTL level • Balan ced propagation delays • All inputs h ave Schmitt-trigger actions • Overvol tage tolerant inputs to 5. 5 V • High noise immunity • CMOS low power dissi pation • ESD protection: • HBM EIA . |
| Manufacture | nexperia |
| Datasheet |
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