74AHCT2G00

INTEGRATED CIRCUITS DATA SHEET www.DataSheet4U.com 74AHC2G00; 74AHCT2G00 2-input NAND gate Product specification 2004 Jan 21 Philips Semiconductors Product specification 2-input NAND gate FEATURES Symmetrical output impedance High noise immunity ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V www.DataSheet4U.com 74AHC2G00; 74AHCT2G00 DESCRIPTION The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device. The 74AHC2G/AHCT2G00 provides the 2-input NAND gate function. – CDM EIA/JESD22-C101 exceeds 500 V. Low power dissipation Balanced propagation delays SOT505-2 and SOT765-1 package Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. PARAMETER propagation delay nA and nB to nY input capacitance power dissipation capacitance per gate CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC2G CL = 15 pF; VCC = 5 V 3.5 1.5 17 AHCT2G 3.6 1.5 18 ns pF pF UNIT 2004 Jan 21 2 Philips Semiconductors Product specification 2-input NAND gate FUNCTION TABLE See note 1. INPUT nA L L ...