DatasheetsPDF.com

74AUP1G09 Datasheet

Part Number 74AUP1G09
Manufacturers NXP
Logo NXP
Description Low-power 2-input AND Gate
Datasheet 74AUP1G09 Datasheet74AUP1G09 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 01 — 15 January 2009 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V.

  74AUP1G09   74AUP1G09






Part Number 74AUP1G09
Manufacturers Diodes
Logo Diodes
Description SINGLE 2 INPUT POSITIVE AND GATE
Datasheet 74AUP1G09 Datasheet74AUP1G09 Datasheet (PDF)

74AUP1G09 SINGLE 2 INPUT POSITIVE AND GATE WITH OPEN DRAIN OUTPUT Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The AUP1G09 is a single AND gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the d.

  74AUP1G09   74AUP1G09







Part Number 74AUP1G09
Manufacturers nexperia
Logo nexperia
Description Low-power 2-input AND gate
Datasheet 74AUP1G09 Datasheet74AUP1G09 Datasheet (PDF)

74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 7 — 14 January 2022 Product data sheet 1. General description The 74AUP1G09 is a single 2-input AND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circu.

  74AUP1G09   74AUP1G09







Low-power 2-input AND Gate

www.DataSheet4U.com 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 01 — 15 January 2009 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple pack.


2009-08-31 : D2111    CA2201    CA2101    FDS4885C    FDS4895C    FDS4897C    ADCLK950    HMC-C062    LMK01000    LMK01010   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)