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74AUP1G125 Datasheet

Part Number 74AUP1G125
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description Low-power buffer/line driver
Datasheet 74AUP1G125 Datasheet74AUP1G125 Datasheet (PDF)

74AUP1G125 Low-power buffer/line driver; 3-state Rev. 02 — 30 June 2006 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across .

  74AUP1G125   74AUP1G125






Part Number 74AUP1G125
Manufacturers Diodes
Logo Diodes
Description SINGLE BUFFER GATE
Datasheet 74AUP1G125 Datasheet74AUP1G125 Datasheet (PDF)

74AUP1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G125 is a single, non-inverting buffer/bus driver, designed for operation over a power supply range of 0.8V to 3.6V. The device has a three-state output that enters a high-impedance state when a high level is applied to the output enable (OE) pin. The device is fully specified.

  74AUP1G125   74AUP1G125







Part Number 74AUP1G125
Manufacturers nexperia
Logo nexperia
Description Low-power buffer/line driver
Datasheet 74AUP1G125 Datasheet74AUP1G125 Datasheet (PDF)

74AUP1G125 Low-power buffer/line driver; 3-state Rev. 9 — 14 January 2022 Product data sheet 1. General description The 74AUP1G125 is a single buffer/line driver with 3-state output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry d.

  74AUP1G125   74AUP1G125







Low-power buffer/line driver

74AUP1G125 Low-power buffer/line driver; 3-state Rev. 02 — 30 June 2006 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G125 provides the single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when OE is HIGH. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-C Class 3A. Exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static pow.


2010-04-28 : CRA04P    74AUP1G373    74AUP1G386    74AUP1G125    74AUP1GU04    W332M64V-XBX    W332M64V-XSBX    W332M72V-XBX    W332M72V-XSBX    A43L0616B   


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